Generally, SiLENSe has no upper limit for forward voltage. However, at higher currents it takes more iterations to get convergence and finally at some bias convergence is lost. Fortunately, for typical strustures convergence is lost only at very high current densities, say 100kA/cm^2 . Since realistics current densities are lower, it is acceptible.
SiLENSe 계산시에 converge되지 않는 bias step이 있을 경우
'Global Parameter' tab에 있는 the maximum iteration number를
200(디폴트)에서 최대 1000회 까지 증가시켜 볼 수 있음
