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High power thin film LED chip design

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: 심규찬
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: 2023-12-03
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첨부파일

Lumileds SpeCLED dvx 파일 첨부



STR 코멘트



Please note it was considerable progress in our understanding of LED simulation. I would like to note the following points:


1. Development of the quantum potential model in SiLENSe. In the original *.sls file, an increased mobility is used to decrease
the p-n junction bias predicted.

2. In SiLENSe, I recommend to select as the active region QW layers only, but not the barriers.

3. In the attached *.dvx file, SiLENSe results are used with 50 K temperature step As the difference in the current density at a
certain bias between 300K and 350K is about 100 times, linear interpolation used in SpeCLED is not so good. I recommend to use
temperature step of 5-20 K range.

4. We have realized that ignoring lateral heat transfer in the submount can lead to dramatic overestimation of the maximum
temperature and lateral variation of the temperature. So the temperature distribution shown in page 5 of the presentation
(http://load.str-soft.com/Data11/SimuLED/Publications/2009_Karpov_WhiteLEDs_presentation.pdf) to be corrected in a manner we did
it in the ThinGaN example supplied with SpeCLED and RATRO (please look "c:\Program Files (x86)\STR IP Holding\SpeCLED RATRO
2008\Examples\ThinGaN\SpeCLED_RATRO\HeatTransferThinFilmFlipChip.pdf" file).

I can prepare new *.dvx file with point 4 corrected, but I need some time for that.

By the way, ThinGaN example supplied with SpeCLED and RATRO includes the similar SiLENSe files with points 2 and 3 corrected.





-SpeCLED 접촉저항 입력 부분

I have realized another point to be fixed in *.dvx file. The specific contact resistances between electrodes and semiconductor are
zero. However, even 1e-5 and 1e-4 Ohm*cm2 for n- and p- sides, respectively (which is quite optimistic assumption), the resulting
current spreading pattern will be more smooth.

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